For integrated circuit manufacturers, one of the several strategies employed for improving integration level and reducing manufacturing cost of integration circuits is the introduction of multi-gate devices (e.g., a multiple gate field-effect transistor, which incorporates more than one gate into a single transistor). The multi-gate device, such as a fin field effect transistor (FinFET), is proposed to replace the conventional planar MOSFET since it is getting harder and harder to reduce the physical dimension of the conventional planar MOSFET.
By forming a three dimensional fin of semiconductor material, and fabricating metal or polysilicon gate structures over the fins, the gate width of the transistor can be longer for a given area, increasing device performance even as the semiconductor processes continue to shrink, and improving density. Standard cell libraries are now implemented using FinFET transistors. However, the use of FinFET transistors in the standard cell methodologies creates additional problems in verification